Semiconductor memory device configured to reduce current consumption associated with critical evaluating of data write operations

ABSTRACT

A semiconductor memory device that utilizes a routing controller and various specific operational modes for reducing current consumption during data write pass operations. The semiconductor memory device includes write pass corresponding to first pad which transfer any one of general data and representative data corresponding to specific mode; and a routing controller routing the representative data to transfer pass corresponding to second pad according to the specific operational mode and upon deviating from the mode, interrupting the routing of the general data to the transfer pass.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to Korean patent application number 10-2007-0091753 filed on Sep. 10, 2007, which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device configured to reduce current consumption associated with critically evaluating data write operations.

In general, when performing write pass testing that evaluates the performance of cells in semiconductor memory device, such as a DRAM, these memory cells are conventionally tested one by one, i.e., tested in series. As these semiconductor memory cells become increasingly more sophisticated and crowded, the these write pass serial testing techniques consequently adversely suffer from unacceptably longer testing times and concomitant increases the cost of these write pass serial testing procedures.

Therefore, new methods and test designs are needed in testing the performance of these ever increasingly complex and crowded semiconductor memory devices. Parallel write pass testing procedures promise the advantage of reducing the testing time and the testing costs. Parallel testing procedures can provide a “pass” decision for a plurality memory cells in the event that all output data in a read operation are found to be the same after writing the same data in the plurality of cells. Likewise parallel testing procedures can provide a “no pass” or “fail” or “poor performance” decision for a plurality of memory cells in the event that output data in a read operation are found to be difference after writing the same data in the plurality of cells. Thereby, parallel testing procedures provide the possibility of reducing the write pass testing time.

In the related conventional art, as shown in FIG. 1, the parallel test mode is entered by making a write pass, that is, a data transfer pass in the write operation.

As depicted in FIG. 1, general data are input from pads DQ0 to DQ3 in a normal mode are buffered via input buffers 10 a to 10 d and are then aligned to be matched with a burst sequence by a write data strobe signal WDQS in data alignment units 11 a to 11 d.

Each aligned general data ALGN_DATA0 to ALGN_DATA3 is subsequently amplified through input/output sense amplifiers 13 a to 13 d and are then transferred to corresponding memory cells via global data lines WGIO0 to WGIO3.

On the one hand, also in the related conventional art, representative data are input from a representative pad DQ0 of the plurality of pads DQ0 to DQ3 in the parallel test mode, are aligned via the input buffer 10 a and the data alignment unit 11 a.

Subsequently, the representative data, ALGN_DATA0, aligned by the data alignment unit 11 a is then routed to multiplexers 12 b to 12 d. The multiplexers 12 b to 12 d, in response to an enabled parallel test signal PARA_TEST, output the aligned representative data ALGN_DATA0 to the corresponding input/output sense amplifiers 13 b to 13 d, respectively. Therefore, in order to write the same data in the plurality of memory cells in the parallel test mode of the related conventional art, only the representative data is input from the representative pad DQ0 of the plurality of pads DQ0 to DQ3 is used.

Accordingly, in the related conventional art, in order to select and transfer any one of the aligned data corresponding to the normal mode and the parallel test mode, for example, the ALGN_DATAO and the ALGN_DATA1, the multiplexers 12 b to 12 d are controlled by the parallel test signal PARA_TEST.

However, even in the write operations of the related conventional art, not the parallel test mode, the aligned general data ALGN_DATAO which is aligned by the data alignment unit 11 a is routed to the multiplexers 12 b to 12 d. This aligned general data ALGN_DATAO routing to the multiplexers 12 b to 12 d is a source of a problem that results in causing an inefficient and consequently unnecessary current consumption to occur during the transfer process of the aligned general data ALGN_DATA0.

Also in the related conventional art, semiconductor memory device, such as a DDR2 SDRAM, generally includes an off chip driver (ODT) controller 14 that are used to control the impedance of a data output driver. Herein, the off chip driver control is understood to mean that the impedance of the data output driver is controlled in order to optimize a current system by measuring either the voltage or the current providing into the data output drive of the memory device interfacing data with various external devices.

Also in the related conventional art, the semiconductor device for the off chip driver control receives the representative data input from the pad DQ0 used for controlling the impedance of the data output driver in an idle mode. Subsequently the representative data is aligned through the data alignment unit 11 a which then transfers the aligned representative data ALGN_DATA0 to the off chip driver controller 14. Further, the off chip driver controller 14 uses the aligned representative data ALGN_DATA0 to output a signal ODT_OUT for controlling the impedance of the data output driver.

In the related conventional art, however, even in the write operation, not the standby mode, the general data ALGN_DATA0 aligned through the data alignment unit 11 a is routed to the off chip driver controller 14 which is a source of a problem that results in causing an unnecessary or inefficient current consumption in the transfer process of the aligned general data ALGN_DATA0.

As described above, in the related conventional art, the general data ALGN_DATA0 aligned in the write operation are unnecessarily routed during other transfer passes. Accordingly, the aligned general data ALGN_DATA0 is unnecessarily toggled which is a source of a problem that leads to unnecessary or inefficient current consumption. This unnecessary current consumption can be a significant factor in the energy consumption of the semiconductor memory device when operating burst write current (IDD4W) operations.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor memory device capable of reducing burst write current consumption.

The present invention provides a semiconductor memory device configured to be capable of reducing unnecessary current consumption brought about by routing of predetermined data to other transfer passes for a parallel test during a write testing operation.

The present invention provides a semiconductor memory device configured to be capable of reducing unnecessary or inefficient current consumption brought about by routing of predetermined data to other transfer passes for controlling impedance of a data output driver during a write operation.

There is provided a semiconductor memory device according to one embodiment of the present invention which includes: write pass corresponding to first pad and transferring any one of general data and representative data corresponding to specific mode; and a routing controller routing the representative data to transfer pass corresponding to second pad according to the specific mode and upon deviating from the specific mode, interrupting the routing of the general data to the transfer pass.

Preferably, the general data are data input in a write operation mode and the representative data are data input in a parallel test mode or a standby mode.

Preferably, the routing controller, when in the parallel test mode, routes the representative data to the transfer pass, and the routing controller, when in the write operation, interrupts the routing of the general data to the transfer pass.

Preferably, the transfer pass includes an off chip driver controller which receives the representative data to control the impedance of a data output driver when in the standby mode.

Preferably, the routing controller, when in the standby mode, routes the representative data to the off chip driver controller, and the routing controller, when in the write operation, interrupts the routing of the general data to the off chip driver controller.

There is provided a semiconductor memory device according to another embodiment of the present invention that includes: first pad receiving first general data; second pad receiving any one of second general data and representative data corresponding to specific modes; data alignment unit aligning the data input from the first and second pad, respectively, being matched with a burst sequence; a routing controller routing the aligned representative data to transfer pass corresponding to the second pad according to the specific mode, and upon deviating from the mode, the routing controller interrupting the routing of the aligned second general data to the transfer pass corresponding to the first pad; multiplexer selecting and transferring any one of the aligned first general data and the aligned representative data routed to the transfer pass in accordance to the specific mode; and sense amplifier each amplifying the aligned second general data and data transferred through multiplexer and transferring the amplified data to global data line.

Preferably, the first and second general data are input to the first and second pads when in the write operation, and the representative data are selectively input to their respective second pads when in a parallel test mode or when in a standby mode.

Preferably, the routing controller, when in the parallel test mode, transfers the aligned representative data to their respective multiplexer and when in the write operation, interrupts the transfer of the second aligned general data to their respective multiplexer.

Preferably, the routing controller includes a logic combination unit which logically combines a the parallel test signal determining the parallel test mode and the aligned representative data or logically combines the parallel test signal and the second general data, and the routing is controller by the logically combination of the logic combination unit.

Preferably, the semiconductor memory device of the present invention includes an off chip driver controller, when in the standby mode, which receives the aligned representative data to control an impedance of a data output driver.

Preferably, the routing controller, when in the standby mode, transfers the aligned representative data to the off chip driver controller and when in the write operation, interrupts the transfer of the aligned second general data to the off chip driver controller.

Preferably, the routing controller includes a logic combination unit which logically combines a ras idle signal determining the standby mode and outputs the aligned representative data or logically combines the ras idle signal and the aligned second general data, and the routing is controller by the logically combination of the logic combination unit.

Preferably, the routing controller interrupts the transfer of the aligned second general data to the multiplexers and to the off chip driver controller when in the write operation, transfers the aligned representative data to the respective multiplexer when in the parallel test mode, and transfers the aligned representative data to the off chip driver controller when in the standby mode.

Preferably, the routing controller includes a first logic combination unit which logically combines a parallel test signal determining the parallel test mode and a ras idle signal determining the standby mode; and a second logic combination unit which logically combines an output of the first logic combination unit and outputs the aligned representative data or the output of the first logic combination unit and the aligned second general data, wherein the routing is controlled by the logically combination of the second logic combination unit.

The multiplexer selects and transfers the first aligned general data when in the write operation and selects and transfers the aligned representative data routed to the transfer pass when in the parallel test mode or in the standby mode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing some data write passes in a conventional semiconductor memory device.

FIG. 2 is a block diagram showing some data write passes in a semiconductor memory device of the present invention.

FIG. 3 is a circuit diagram showing one example of a routing controller 22 of FIG. 2.

FIG. 4 is a circuit diagram showing another example of the routing controller 22 of FIG. 2.

FIG. 5 is a waveform diagram for explaining a data transfer according to operation modes in the semiconductor memory device of the present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention interrupts a routing of predetermined data to other transfer passes corresponding to specific modes in a write operation, making it possible to reduce current consumption due to an unnecessary toggling of data.

Specifically, a semiconductor memory device of the present invention includes a plurality of input buffers 20 a, 20 b, 20 c, 20 d, a plurality of data alignment units 21 a to 21 d, a routing controller 22, a plurality of multiplexers 23 b to 23 d, and a plurality of input/output sense amplifiers 24 a to 24 d, as shown in FIG. 2.

Each input buffer 20 a to 20 d buffers and outputs data input from each pad DQ0 to DQ3.

Each data alignment unit 21 a to 21 d aligns the data buffered in each input buffer 20 a to 20 d to be matched with a burst sequence to output the data buffered in each input buffer 20 a to 20 d as the respective alignment data ALGN_DATA0 to ALGN_DATA3.

The routing controller 22 routes a representative alignment data ALGN_DATA0 to the transfer passes corresponding to the other pads DQ1 to DQ3 in a specific mode, and upon deviating from the specific mode, interrupts the routing of the general alignment data ALGN_DATA0 to the transfer passes.

Herein, the operation of the routing controller 22 is controlled the operation by receiving a control signal CTRL corresponding to the specific modes, wherein when the specific modes is a parallel test mode, the parallel test signal PARA_TEST may be used as a control signal CTRL. Also, the representative alignment data ALGN_DATA0 is understood to mean the alignment of data input from the pad DQ0 in the specific mode and the general alignment data ALGN_DATA0 is understood to mean the alignment of data input from the pad DQ0 in the a normal mode.

Each multiplexer 23 b to 23 d selects and transfers any one of the alignment data ALGN_DATA1 to ALGN_DATA3 and the alignment data ALGN_DATA_EX routed from the routing controller 22 in accordance to the parallel test signal PARA_TEST in the parallel test mode.

Each input/output sense amplifier 24 a to 24 d amplifies the alignment data ALGN_DATA0 to ALGN_DATA3 to transfer the respective amplified alignment data ALGN_DATA0 to ALGN_DATA3 through the respective global data lines WGIO0 to WGIO3.

The semiconductor memory device having such a constitution is designed to interrupt the transfer of the general alignment data ALGN_DATA_EX to each multiplexer 23 b to 23 d via the routing controller 22 in the write operation. The routing controller 22 may be constituted by a circuit as in FIG. 3 as one example. In FIG. 3, assume that 4 bit data are sequentially input from the respective input/output pads DQ0 to DQ3 and the alignment data ALGN_DATA0 corresponds to the alignment data ALGN_DATA0_Q0 to ALGN_DATA0_Q3.

Referring to FIG. 3, the routing controller 22 includes logic combination unit that logically combines the control signal CTRL with the respective alignment data ALGN_DATA0_Q0 to ALGN_DATA0_Q3. The logic combination unit is shown to include a NAND gate NA1 which NAND-combines the control signal CTRL and the respective alignment data ALGN_DATA0_Q0; and an inverter IV1 which inverts the output of the NAND gate NA1 into the alignment data ALGN_DATA_EX_Q0. The logic combination unit is shown to also include a NAND gate NA2 which NAND-combines the control signal CTRL with the respective alignment data ALGN_DATA0_Q1; and an inverter IV2 which inverts the output of the NAND gate NA2 into the respective alignment data ALGN_DATA_EX_Q1. The logic combination unit is shown also to include a NAND gate NA3 which NAND-combines the control signal CTRL with the respective alignment data ALGN_DATA0_Q2; and an inverter IV3 which inverts the output of the NAND gate NA3 into the respective alignment data ALGN_DATA_EX_Q2. The logic combination unit is shown also to include a NAND gate NA4 which NAND-combines the control signal CTRL with the respective alignment data ALGN_DATA0_Q3; and an inverter IV4 which inverts the output of the NAND gate NA4 into the respective alignment data ALGN_DATA_EX_Q3.

As depicted in FIG. 2, the semiconductor memory device of the present invention may further include an off chip driver 25 which receives, when in a standby mode, the representative alignment data ALGN_DATA_EX to output a signal ODT_OUT for controlling the impedance of a data output driver. A ras idle signal RAS_IDLE may be used to correspond to the standby mode which is then used as the control signal CTRL to direct the routing controller 22 to interrupt the transfer of the general alignment data ALGN_DATA_EX to the off chip driver controller 25 in the write operation. The ras idle signal RAS_IDLE may be used as the control signal CTRL to direct the routing controller 22 to interrupts the transfer of the general alignment data ALGN_DATA_EX to the respective multiplexers 23 b to 23 d, which are also directed by the parallel test signal PARA_TEST, and the ras idle signal RAS_IDLE may be used as the control signal CTRL to direct the off chip driver controller 25 in the write operation.

In the write operation as depicted in FIGS. 2 and 4, the routing controller 22 may interrupt the transfer of the alignment data ALGN_DATA_EX to the respective multiplexers 23 b to 23 d and the off chip driver controller 25.

Referring to FIG. 4, the routing controller 22 includes a NOR gate NR1 which NOR-combines a parallel test signal PARA_TEST and the ras idle signal RAS_IDLE, an inverter IV5 which inverts the output of the NOR gate NR1, a NAND gate NA5 which NAND-combines the output of the inverter IV5 and the alignment data ALGN_DATA0_DQ; an inverter IV6 which inverts the output of the NAND gate NA5 into an alignment data ALGN_DATA_EX_Q0; a NAND gate NA6 which NAND-combines the output of the inverter IV5 and the alignment data ALGN_DATA0_Q1; an inverter IV7 which inverts the output of the NAND gate NA6 into the alignment data ALGN_DATA_EX_Q1; a NAND gate NA7 which NAND-combines the output of the inverter IV5 and the alignment data ALGN_DATA0_Q2; an inverter IV8 which inverts the output of the NAND gate NA7 into the alignment data ALGN_DATA_EX_Q2; a NAND gate NA8 which NAND-combines the output of the inverter IV5 and the alignment data ALGN_DATA0-Q3; and an inverter IV9 which inverts the output of the NAND gate NA8 into the alignment data ALGN_DATA_EX_Q3.

Hereinafter, the operation of the semiconductor memory device of the present invention will be described with reference to FIG. 5.

First, when the control signal CTRL is a low level the semiconductor memory device can be set in the write operation mode. In the write operation mode, general data Q0 to Q3 are sequentially input from the data input/output pad DQ0 and aligned as ALGN_DATA0_Q0 to ALGN_DATA0_Q3 through a data alignment unit 21 a. Accordingly, the general alignment data ALGN_DATA0_Q0 to ALGN_DATA0_Q3 are fixed at a low level (Low Fix) through the routing controller 22. It is important to note that in the write operation, the general alignment data ALGN_DATA0_Q0 to ALGN_DATA0_Q3 are not routed to the multiplexers 23 b to 23 d and not routed to the off chip driver controller 25 through the routing controller 22.

When the control signal CTRL is a high level, the semiconductor memory device can be set in the parallel test mode. In the parallel test mode or a state, the representative alignment data ALGN_DATA0_Q0 to ALGN_DATA0_Q3 are output as the representative alignment data ALGN_DATA_EX_Q0 to ALGN_DATA_EX_Q3 through the routing controller 22. Further the representative alignment data ALGN_DATA_EX_Q0 to ALGN_DATA_EX_Q3 are then transferred to the input/output sense amplifiers 24 b to 24 d through the multiplexers 23 b to 23 d.

When the control signal CTRL is a high level, the semiconductor memory device can be set in the standby mode. In the standby mode or state, the representative alignment data ALGN_DATA_Q0 to ALGN_DATA_Q3 are output as the representative alignment data ALGN_DATA_EX_Q0 to ALGN_DATA_EX_Q3 through the routing controller 22 and input to the off chip driver controller 25.

As described above, the semiconductor memory device of the present invention interrupts the routing of the predetermined data to the other transfer passes for the specific operational modes in the write operation.

As one example, in the parallel test mode, the representative alignment data ALGN_DATA0 input to the predetermined pad DQ0 and aligned through the data alignment unit 11 a is routed to the respective multiplexers 23 b to 23 d by the routing controller 22. This interrupts the write operation which routes of the general alignment data ALGN_DATA0 input through the same pad DQ0 and aligns the general alignment data ALGN_DATA0 through the data alignment unit 21 a to the respective multiplexers 23 b to 23 d using the routing controller 22. In other words, in the write operation, since the routing of the general alignment data ALGN_DATA0 to the other write passes for the parallel test mode is interrupted, the unnecessary toggling of the alignment data ALGN_DATA0 in the write operation is reduced, making it possible to obtain to reduce current consumption during this operation.

Also, in the standby mode, the representative alignment data ALGN_DATA0 is transferred to the off chip driver 25, which interrupts the transfer of the general alignment data ALGN_DATA0 through the routing controller 22 of the write mode operation. In other words, in the write operation, since the general alignment data ALGN_DATA0 is not transferred to the circuit for controlling the impedance of the data output driver, the unnecessary toggling of the alignment data ALGN_DATA0 is reduced in the write operation, making it possible to reduce current consumption.

As above, the semiconductor memory device of the present invention can reduce the current consumption by the aligned data ALGN_DATA0 in the write operation, making it possible to obtain an effect that the operating burst write current can be reduced.

Also, the present invention interrupts the routing of the predetermined data to other transfer passes other than the corresponding write pass to reduce the current consumption due to the data, making it possible to reduce the operating burst write current.

Also, the present invention interrupts the routing of the predetermined data to the other write passes for the parallel test mode in the write operation to reduce the unnecessary toggling of the data. Thereby making it possible to reduce current consumption

Also, the present invention interrupts the routing of the predetermined data to the off chip driver controller for controlling the impedance of the data output driver in the write operation to reduce the unnecessary toggling of the data. Thereby making it possible to reduce current consumption.

Those skilled in the art will appreciate that the specific embodiments disclosed in the foregoing description may be readily utilized as a basis for modifying or designing other embodiments for carrying out the same purposes of the present invention. Those skilled in the art will also appreciate that such equivalent embodiments do not depart from the spirit and scope of the invention as set forth in the appended claims. 

1. A semiconductor memory device, comprising: write pass corresponding to first pad and transferring any one of general data and representative data corresponding to specific mode; and a routing controller routing the representative data to transfer pass corresponding to second pad according to the specific mode and upon deviating from the specific mode, interrupting the routing of the general data to the transfer pass.
 2. The semiconductor memory device set forth in claim 1, wherein the general data are data input in a write operation mode and the representative data are data input in a parallel test mode or a standby mode.
 3. The semiconductor memory device set forth in claim 2, wherein the routing controller, when in the parallel test mode, routes the representative data to the transfer pass and the routing controller, when in the write operation mode, interrupts the routing of the general data to the transfer pass.
 4. The semiconductor memory device set forth in claim 2, wherein the transfer pass include an off chip driver controller which in the standby mode receives the representative data to control impedance of a data output driver.
 5. The semiconductor memory device set forth in claim 4, wherein the routing controller, when in the standby mode, routes the representative data to the off chip driver controller and the routing controller, when in the write operation, interrupts the routing of the general data to the off chip driver controller.
 6. A semiconductor memory device, comprising: first pad receiving first general data; second pad receiving any one of second general data and representative data corresponding to specific mode; data alignment unit aligning the data input from the first and second pad, respectively, being matched with a burst sequence; a routing controller routing the aligned representative data to transfer pass corresponding to the first pad and the second pad directed by the specific mode, and upon deviating from the specific mode, and interrupting the routing of the aligned second general data to the transfer pass corresponding to the first pad; multiplexer selecting and transferring any one of the aligned first general data and the aligned representative data according to the specific mode; and sense amplifier amplifying the aligned second general data and data transferred through the multiplexer and transferring the amplified data to global data line.
 7. The semiconductor memory device set forth in claim 6, wherein when in the write operation the first and second general data are input to the first and second pad respectively and when in a parallel test mode or a standby mode the representative data are representatively input from the second pad.
 8. The semiconductor memory device set forth in claim 7, wherein when in the parallel test mode the routing controller transfers to the aligned representative data to the respective multiplexer and when in the write operation the routing controller interrupts the transfer of the aligned second general data to the respective multiplexer.
 9. The semiconductor memory device set forth in claim 8, wherein the routing controller includes a logic combination unit which logically combines a parallel test signal determining the parallel test mode and the aligned representative data or logically combines the parallel test signal and the aligned second general data, and the routing is controlled by the logically combination of the logic combination unit.
 10. The semiconductor memory device set forth in claim 7, further comprising an off chip driver controller, when in the standby mode, which receives the aligned representative data to control an impedance of a data output driver.
 11. The semiconductor memory device set forth in claim 10, wherein when in the standby mode the routing controller transfers the aligned representative data to the off chip driver controller and when in the write operation mode the routing controller interrupts the transfer of the aligned second general data to the off chip driver
 12. The semiconductor memory device set forth in claim 11, wherein the routing controller includes a logic combination unit which logically combines a ras idle signal determining the standby mode and the aligned representative data or logically combines the ras idle signal and the aligned second general data, and the routing is controlled by the logically combination of the logic combination unit.
 13. The semiconductor memory device set forth in claim 11, wherein when in the write operation the routing controller interrupts the transfer of the aligned second general data to the multiplexer and to the off chip driver controller; when in the parallel test mode the routing controller transfers the aligned representative data to the respective multiplexer; and when in the standby mode the routing controller transfers the aligned representative data to the off chip driver controller.
 14. The semiconductor memory device set forth in claim 13, wherein the routing controller includes: a first logic combination unit which logically combines a parallel test signal determining the parallel test mode and a ras idle signal determining the standby mode; and a second logic combination unit which logically combines an output of the first logic combination unit and the aligned representative data or combines the output of the first logic combination unit and the second general data, wherein the routing is controlled by the logically combination of the second logic combination unit.
 15. The semiconductor memory device set forth in claim 6, wherein when in the write operation the multiplexer selects and transfers the aligned first general data; and when in the parallel test mode or the standby mode the multiplexer selects and transfers the aligned representative data routed to the transfer pass. 